In the prior art it is known to design parity predict networks for detecting errors in N'th power Galois arithmetic gates. In the publication "A Cellular-Array Multiplier for GF(2.sup.m)," B. A. Laws, Jr., et al IEEE Transactions on Computers, Dec. 1971, pp. 1573-1578, with particular reference to FIGS. 5 and 6 and the pertinent discussion thereof, there are disclosed methods of designing parity predict networks for a cellular array N'th power Galois multiplication gate. This method of B. A. Laws, et al, is applicable only to a cellular array (as distinguished from a combinatorial array to which the present invention is directed), and, accordingly, is not applicable to all N'th power Galois multiplication gates while yet requiring a rigorous mathematical treatment of the logic terms of the cellular array to determine the appropriate construction of the parity predict network. In contrast, the present invention is directed toward the application of a straight-forward algorithm that by a visual inspection of the manner in which the outputs of the 1 through m-1 levels of parity trees are coupled as inputs to the output, m-level parity trees determines the particular first level parity tree's outputs that are coupled as inputs to the parity predict network.